1. Field
Exemplary embodiments of the present invention relate to a memory device and a method for operating the same, and, more particularly, to a technology related to an address of a memory device.
2. Description of the Related Art
Basically, a memory device employs a time multiplexed addressing method. In other words, when an address is input together with a row address strobe (RAS) signal, the memory device recognizes the address as a row address and activates a row selected from a plurality of rows in a cell array. Also, when an address is input together with a column address strobe (CAS) signal, the memory device recognizes the address as a column address and accesses data of columns selected from a plurality of columns corresponding to the selected row.
FIG. 1 is a diagram illustrating a part related to the input of an address in a conventional memory device.
Referring to FIG. 1, the memory device includes a command input circuit 110, a command decoder 120, an address input circuit 130, and an address selection unit 140.
The command input circuit 110 receives command signals input from an exterior, latches the input command signals in synchronization with a clock CLK, and provides the latched signals to the command decoder 120. The command signals may include a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, a chip select signal CS, and the like.
The command decoder 120 decodes the command signals received from the command input circuit 110 and generates internal command signals ACT, PCG, RD, and WT. The internal command signals may include an active signal ACT, a precharge signal PCG, a read signal RD, a write signal WT, and the like.
The address input circuit 130 receives multi-bit addresses A<0:N> input from an exterior, latches the input addresses in synchronization with the clock CLK, and provides the latched addresses to the address selection unit 140. The address input circuit 130 includes buffers and latches corresponding to the number of bits of the addresses A<0:N>.
The address selection unit 140 selects addresses ROW_A<0:N> or column addresses COL_A<0:M> to which the addresses received through the address input circuit 130 are provided under the control of the command decoder 120. When a command decoded by the command decoder 120 requires a row address, the address selection unit 140 provides the address received from the address input circuit 130 as the row addresses ROW_A<0:N>. When a command decoded by the command decoder 120 requires a column address, the address selection unit 140 provides the address received from the address input circuit 130 as the column addresses COL_A<0:M>. For example, when the internal command signal activated by the command decoder 120 is the active signal ACT, the address selection unit 140 provides the address received from the address input circuit 130 as the row addresses ROW_A<0:N>. Furthermore, when the internal command signal activated by the command decoder 120 is the read signal RD or the write signal WT, the address selection unit 140 provides the address received from the address input circuit 130 as the column addresses COL_A<0:M>.
In general, the number of bits of the row addresses ROW_A<0:N> used in the memory device is larger than the number of bits of the column addresses COL_A<0:M>. For example, the row addresses ROW_A<0:N> may be 14 bits (N=13) and the column addresses COL_A<0:M> may be 10 bits (M=9). Thus, when the row addresses ROW_A<0: N> are input to the memory device, all the buffers and the latches in the address input circuit 130 need to operate. However, when the column addresses COL_A<0:M> are input to the memory device, all the buffers and the latches in the address input circuit 130 may not need to operate. Since the addresses are applied to the memory device by a memory controller, it may be difficult for the memory device to recognize the time at which an address is applied and the type of the address. Therefore, even when the column addresses are input to the memory device, unnecessary buffers, latches and the like operate, thereby resulting in wasteful current consumption.